Ultra-low power encryption engine for wireless implantable medical devices

Wireless implantable medical devices are expected to perform cryptographic processing at an absolutely low level of power consumption. This paper presents the design of an ultra-low power ASIC core implementing the PRESENT encryption algorithm. To minimize power consumption, subthreshold CMOS logic is adopted. To implement robust combinational logic (S-Boxes) in PRESENT at subthreshold, a multiplexor-tree architecture based on CMOS transmission gates is proposed. Our post-layout simulations show that our PRESENT core consumes around 50 nW at 0.35V supply voltage at 25 kHz clock frequency, proving the feasibility of ultra-low power encryption.