Title :
Analysis and design of fully integrated very low quiescent current LDOs
Author :
Valapala, Harish ; Furth, Paul M.
Author_Institution :
Klipsch Sch. of Electr. & Comput. Eng., New Mexico State Univ., Las Cruces, NM, USA
Abstract :
We introduce two extremely low quiescent current (IQ) low-dropout (LDO) voltage regulators. The Low IQ-LDO (LIQ-LDO) has a minimum ground current of 13 μA and is designed for a maximum load current of 50 mA. The Micro IQ-LDO (MIQ-LDO) has a minimum ground current of 1.2 μA and is designed for a maximum load current of 5 mA. Detailed pole/zero analysis is performed to aid in the design of the LDOs. Two LHP zeros cancel the two non-dominant poles which extend the bandwidth and improve transient response. Both designs are fully integrated, stabilized with an on-chip capacitive load of 100 pF. A process-independent figure of merit (FOM) is proposed to compare LIQ-LDO and MIQ-LDO with other published work.
Keywords :
network analysis; network synthesis; voltage regulators; LHP zeros cancel; LIQ-LDO; MIQ-LDO; current 1.2 muA; current 13 muA; current 5 mA; current 50 mA; extremely low quiescent current; fully integrated very low quiescent current LDO; low IQ-LDO; low-dropout voltage regulators; maximum load current; minimum ground current; nondominant poles; on-chip capacitive load; pole/zero analysis; process-independent figure of merit; transient response; Capacitors; Mathematical model; Poles and zeros; Radio frequency; Resistors; Transient analysis; Transistors;
Conference_Titel :
Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on
Conference_Location :
Boise, ID
Print_ISBN :
978-1-4673-2526-4
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2012.6291999
