A Pipelining Hardware Implementation of H.264 Based on FPGA

A two-dimensional discrete cosine transform (DCT) module for the JPEG image compression system is designed. Considering the compromise of resource and speed in the FPGA chip, two same 1D-DCT module are reused to complete the FPGA design of 2D-DCT. The pipelining levels in the module are also analyzed and optimized. Simulation and test results for the whole system based on EP1C6Q240C8 show that it can perform the integer DCT of 4 × 4 block in twelve clock cycles and 10% resource consumption rate. It provides a exploring attempt and a positive reference on the JPEG encoder system IP core design and their FPGA implementation.