A digitally calibrated current-steering DAC with current-splitting array

Author

Long Cheng ; Chi-Xiao Chen ; Fan Ye ; Ning Li ; Jun-yan Ren

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2012

fDate

5-8 Aug. 2012

Firstpage

278

Lastpage

281

Abstract

The current-splitting architecture for the current-steering DAC can reduce the area of the current source array greatly. A background calibration technique for current-steering digital-to-analog (DAC) with the current-splitting array is presented. The proposed calibration technique can eliminate mismatch errors for both the upper bits array and the lower bits array in the background. A 14-bit current-steering DAC is fabricated in a 0.18μm CMOS process. The SFDR can be improved more than 20dB. The DAC achieves more than 80dB SFDR at 2MHz for a 200MS/s sampling rate. The active area is 1.26mm² and power consumption is 125mW.

Keywords

CMOS integrated circuits; calibration; constant current sources; digital-analogue conversion; integrated circuit measurement; radiofrequency integrated circuits; CMOS process; SFDR; current-splitting source array; digital-to-analog circuit; digitally calibrated current-steering DAC; frequency 2 MHz; lower bits array; mismatch error elimination; power 125 mW; power consumption; size 0.18 mum; upper bits array; word length 14 bit; Arrays; CMOS integrated circuits; Calibration; Clocks; Redundancy; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on

Conference_Location

Boise, ID

ISSN

1548-3746

Print_ISBN

978-1-4673-2526-4

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2012.6292011

Filename

6292011