DocumentCode :
3204627
Title :
HK-NUCA: Boosting Data Searches in Dynamic Non-Uniform Cache Architectures for Chip Multiprocessors
Author :
Lira, Javier ; Molina, Carlos ; Gonzalez, Adriana
Author_Institution :
Dept. of Comput. Archit., Univ. Politec. de Catalunya, Barcelona, Spain
fYear :
2011
fDate :
16-20 May 2011
Firstpage :
419
Lastpage :
430
Abstract :
The exponential increase in the cache sizes of multicore processors (CMPs) accompanied by growing on-chip wire delays make it difficult to implement traditional caches with single and uniform access latencies. Non-Uniform Cache Architecture (NUCA) designs have been proposed to address this problem. NUCA divides the whole cache memory into smaller banks and allows nearer cache banks to have lower access latencies than farther banks, thus mitigating the effects of the cache´s internal wires. Traditionally, NUCA organizations have been classified as static (S-NUCA) and dynamic (D-NUCA). While in S-NUCA a data block is mapped to a unique bank in the NUCA cache, D-NUCA allows a data block to be mapped in multiple banks. Besides, D-NUCA designs are dynamic in the sense that data blocks may migrate towards the cores that access them most frequently. Recent works consider D-NUCA as a promising design, however, in order to obtain significant performance benefits, they used a non-affordable access scheme mechanism to find data in the NUCA cache. In this paper, we propose a novel and implementable data search algorithm for D-NUCA designs in CMP architectures, which is called HK-NUCA (emph{Home Knows where to find data within the NUCA cache}). It exploits migration features by providing fast and power efficient accesses to data which is located close to the requesting core. Moreover, HK-NUCA implements an efficient and cost-effective search mechanism to reduce miss latency and on-chip network contention. We show that using HK-NUCA as data search mechanism in a D-NUCA design reduces about 40% energy consumed per each memory request, and achieves an average performance improvement of 6%.
Keywords :
cache storage; energy consumption; microprocessor chips; CMP architecture; HK-NUCA; NUCA cache; cache memory; chip multiprocessor; data block mapping; data searching; dynamic nonuniform cache architecture; dynamic-NUCA; energy consumption; home knows-NUCA; implementable data search algorithm; miss latency reduction; nonaffordable access scheme mechanism; nonuniform cache architecture design; on-chip network contention reduction; on-chip wire delays; static-NUCA; Algorithm design and analysis; Computer architecture; Energy consumption; Organizations; Program processors; System-on-a-chip; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel & Distributed Processing Symposium (IPDPS), 2011 IEEE International
Conference_Location :
Anchorage, AK
ISSN :
1530-2075
Print_ISBN :
978-1-61284-372-8
Electronic_ISBN :
1530-2075
Type :
conf
DOI :
10.1109/IPDPS.2011.48
Filename :
6012812
Link To Document :
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