Hybrid continuous-time/discrete-time circuit techniques for the efficient implementation of wideband ΣΔ ADCs

This paper discuses the use of hybrid continuous-time/discrete-time ΣΔ modulators for the implementation of high-efficiency wideband analog-to-digital converters. Two alternative implementations of multi-rate cascade architectures are studied and compared with conventional single-rate continuous-time topologies. The effect of three error mechanisms is considered, namely: mismatch, finite dc gain error and finite gain-bandwidth product. In all cases, closed-form expressions are derived for the nonideal in-band noise power of all ΣΔ modulators under study, giving an analytical relation between their system-level performance and the corresponding circuit-level error parameters. Time-domain behavioral simulations are in good agreement with theoretical predictions, demonstrating the validity of the presented approach.