Operational calibration of mixed-signal integrated circuits in hostile environments

This paper outlines a technique for operational calibration of mixed-signal integrated circuits (IC) using a configurable analog transistor (CAT). The robustness obtained using this technique show a significant improvement over conventional approaches by using a CAT in the most appropriate sections of the design. This approach demonstrates significant benefits for operational calibration compared to traditional design techniques without requiring an excessive area overhead to achieve it. This technique can be used equally well to address variations across an integrated circuit for individual devices or to match specific pairs of devices in a circuit. An increasing problem with decreasing process technology sizes for the analog and mixed signal designer is the intrinsic variability of devices. An important distinction with previous work in our approach is the ability to modify critical devices after manufacture, thereby giving designers the ability to not only tune for optimal performance, but also to improve the overall circuit yield by bringing variable devices back into the required specification. This is particularly helpful in remote or hostile environments where calibration and repair have been particularly problematic. The concept presented in this paper is to provide a mechanism whereby a transistor can be configured to improve the accuracy of the performance or yield by adding an incremental width to the transistor controlled by the user. It is important to state that the definition of the incremental widths is tailored to the circuit application and process and is used to calibrate the devices after manufacture. The approach is designed to achieve optimal adjustability for a particular process and set of design constraints. The architecture of the CAT is divided into 4 sections. The first section is the main transistor, the second is the (much smaller) incremental sections, which are used to obtain the tuned overall transistor size, the third is the switche- s to control the incremental transistors and finally there is a digital memory to store the individual configuration for each CAT device. The devices can be identified and configured using this approach after manufacture. The structure of the example CAT is implemented using a stackable approach where the transistors M1-M4 are aligned vertically, with each transmission gate sandwiched between each main transistor to minimize the connection lengths. This approach is scaleable to any reasonable number of smaller configuration transistors. The design process for using the new CAT device is twofold. The first stage is to identify the devices which are most sensitive to degradation. This is done during the schematic design phase using Monte Carlo analysis of the circuit including process variations. Once the critical devices have been identified, they are replaced with CAT devices so that the overhead of configuration is minimized, and the devices can be optimally modified on IC test after manufacture.