Title :
RSA encryption/decryption in wireless networks using an efficient high speed multiplier
Author :
Thapliyal, Himanshu ; Kamala, R.V. ; Srinivas, M.B.
Author_Institution :
Center for VLSI & Embedded Syst. Technol., Int. Inst. of Inf. Technol., Hyderabad, India
Abstract :
This paper proposes a faster RSA encryption/decryption circuit utilizing a high speed multiplier architecture. The proposed two´s complement N XN bit multiplier architecture is based on two concepts: the partial products can be generated in parallel with a delay of d; and thereafter the addition can be reduced to log2N steps. The most significant aspect of the proposed RSA hardware is that any future proposed efficient adder can be implemented in the proposed multiplier, without changing the original hardware architecture, thereby improving its efficiency to a great extent. The coding of the RSA is done in Verilog HDL and the FPGA synthesis is done using Xilinx libraries. The result shows that the RSA hardware implemented using the proposed architecture is faster than RSA hardware implemented using the traditional multiplication algorithm.
Keywords :
cryptography; field programmable gate arrays; hardware description languages; multiplying circuits; radio access networks; telecommunication security; FPGA synthesis; RSA coding; RSA encryption/decryption; RSA hardware implementation; Verilog HDL; addition step reduction; high speed multiplier; parallel partial products generation; two´s complement N XN bit multiplier; wireless networks; Circuits; Clocks; Cryptography; Embedded system; Hardware design languages; Intelligent networks; Privacy; Propagation delay; Very large scale integration; Wireless networks;
Conference_Titel :
Personal Wireless Communications, 2005. ICPWC 2005. 2005 IEEE International Conference on
Print_ISBN :
0-7803-8964-6
DOI :
10.1109/ICPWC.2005.1431378