A latency-hiding scheme for multiprocessors with buffered multistage networks

Multistage networks for large-scale shared-memory multiprocessors are buffered to increase the throughput and hide the latency. This is achieved by pipelining consecutive memory requests from the same processor. However, unrestrictive pipelining may violate strict memory consistency models such as sequential consistency since memory requests are not guaranteed to be performed in program order. The author proposes and evaluates a novel access ordering scheme that allows the processors to pipeline memory requests under the sequential consistency model. This is achieved by access ordering mechanisms at memory that detect when a request arrives out of order. Simulations show that the scheme manages to improve the processor utilization significantly by hiding network latency through pipelining