A two stage and three stage CMOS OPAMP with fast settling, high DC gain and low power designed in 180nm technology

Two Stage Opamp : An analog to digital converter (ADC) uses switched capacitor stages that settle in two steps. The first step of settling places charge onto the load capacitance using charge pumps, and the second fulfills the settling requirements using negative feedback. The key factor is to establish the optimum combination of gm2/gm1 & Cl/Cc. So, required accuracy & settling time can be established with minimum power consumption. An experimental prototype fabricated in a 0.18um CMOS UMC tech. using cadence requires power consumption of 50μW for Cload=5pf. Typical measured results are 75 dB gain, UGB of 16 MHz, 80ns settling time, PM 60 deg, SR is +6/-6V/us, CMRR is 90dB. The chip active area is about 45 μm X 35 μm. Three stage CMOS opamp: The three stage CMOS opamp with NMC technique is also designed. Simulated results are DC Gain of 90dB, Unity Gain frequency 30MHz, Power consumption 300 μW, Settling Time 150 ns with Cload 1pf. In this paper a novel time domain design methodology for three stage NMC amplifiers was proposed.