Low-spur technique for Integer-N phase-locked loop

Author

Liao, Te-Wen ; Su, Jun-Ren ; Hung, Chung-Chih

Author_Institution

Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2012

fDate

5-8 Aug. 2012

Firstpage

546

Lastpage

549

Abstract

In this paper, we presents a low-spur phase locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator (VCO) in order to reduce the reference spur at the output of the PLL. A new random clock generator is presented to perform a random selection of phase frequency detector (PFD) control for charge pump at locked state. The proposed frequency synthesizer was fabricated in TSMC 0.18-μm CMOS process. The PLL has achieved the phase noise of -105 dBc/Hz at 1MHz offset frequency and reference spurs below -72dBc.

Keywords

CMOS integrated circuits; charge pump circuits; frequency synthesizers; phase detectors; phase locked loops; phase noise; voltage-controlled oscillators; CMOS process; PFD control; PLL system; VCO; charge pump; control voltage; frequency 1 MHz; integer-N phase-locked loop; locked state; low-spur frequency synthesizer; low-spur phase locked loop system; low-spur technique; offset frequency; periodic ripples; phase frequency detector control; phase noise; random clock generator; random selection; reference spur; size 0.18 mum; voltage-controlled oscillator; wireless applications; CMOS integrated circuits; Charge pumps; Clocks; Frequency synthesizers; Generators; Phase locked loops; Voltage-controlled oscillators; PLL; Synthesizer; low spur;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on

Conference_Location

Boise, ID

ISSN

1548-3746

Print_ISBN

978-1-4673-2526-4

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2012.6292078

Filename

6292078