Jitter in ultra-low power audio-range PLLs

This paper investigates phase jitter in an ultra-low power Phase-Locked Loop (PLL). The core of the presented PLL is a current controlled relaxation oscillator, which generates a sawtooth shaped output. Expressions for the cycle-to-cycle jitter caused by the ramp current noise as well as the voltage noise present on the two rails of the sawtooth (V_dd and V_ref) are derived. The theoretical results reveal that the current noise establishes a lower bound for jitter, which scales as the inverse of the square root of the selected ramp current. The PLL has been fabricated in 0.5 μm CMOS technology and targets an output range of 10-150 kHz. The integrated circuit dissipates between 0.8-1.8 μW of power (V_dd=3 V) and yields relative phase jitter values between 0.11% and 0.14%. These numbers are approximately 70% larger than the derived lower bound.