Title :
FIFO locked loop control system
Author :
Bassan, Fabio Renato ; de Camargo Angeli, B.C. ; de Barros, Luis Paulo F. ; Mobilon, Eduardo
Author_Institution :
Opt. Syst. - Electron. & Microelectron., CPqD - Telecom R&D Centre, Campinas, Brazil
Abstract :
In this paper we present a methodology for the development of a circuit to control the reading frequency of a First In First Out (FIFO) memory based on the monitoring of its filling level, with applications in data communication protocol justification architectures for tributary signal mapping and demapping.
Keywords :
data communication; memory cards; protocols; FIFO locked loop control system; data communication protocol justification architectures; filling level monitoring; first in first out memory; reading frequency; tributary signal demapping; tributary signal mapping; Control systems; Equations; Filling; Frequency control; Mathematical model; Payloads; Pulse width modulation;
Conference_Titel :
Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on
Conference_Location :
Boise, ID
Print_ISBN :
978-1-4673-2526-4
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2012.6292083
