A novel offset cancellation technique for dynamic comparator latch

This paper presents a novel architecture of ultra-low offset comparator latch using on-chip calibration to compensate the process variation. The proposed technique compensates the variation in process parameters such as W/L, μCOX and threshold voltage independently by considering the intrinsic behavior of the MOS transistors without using power-hungry complicated circuits on measuring the transistor characteristics. Monte Carlo post-layout HSPICE simulations were carried out with 100 runs to evaluate the performance of the comparator latch. Experimental results show that when comparing with state-of-the-art pre-amplifier-less architectures, the standard deviation of the input voltage offset is reduced by more than 75% over a range of 400mV difference of the common mode input voltage.