Architecture optimization of a finite impulse response filter using toggle-based power estimation

In this paper different methods of implementing finite impulse response (FIR) filters have been discussed. The advantages and disadvantages of several architectures and of the circuit modeling were presented using a standard toggle-based method for the circuit power estimation, gate-level simulations and synthesis. We showed that we can achieve up to 60% power reduction from the beginning by carefully selecting the right architecture and optimizing the VHDL code description of the module. The analysis was made based on the unity delay model and not on the physical extracted layout for a 150 nm technology.