Overhead minimization techniques for digital phase-locked loop frequency synthesizer

One emerging trend of implementing phase locked loop (PLL) based frequency synthesizers is to leverage digital signal processing in the loop filtering for more flexibility, scalability and smaller silicon area. This paper examines the pros and cons of such digital-intensive PLL architecture, and discusses techniques to minimize its overhead in terms of implementation cost and performance degradation. A hardware prototype in 65nm CMOS that synthesizes frequencies over 600-800 MHz is shown to prove the effectiveness the proposed overhead minimization techniques.