Gain increasing techniques for CMOS folded cascode LNAs at low voltage and low power operations

Design and simulated results of a fully integrated 5GHz CMOS LNAs are presented. To design these LNAs, the parasitic input resistance of a MOSFET is converted to 50Ω by a simple L-C network, hence eliminating the need for source degeneration. As it is analytically shown, this is because the former methods enhance the gain of the LNA by a factor that is inversely proportional to MOSFET´s input resistance. By employing the folded cascode technique, the proposed LNA can operate at a reduced supply voltage, high gain and ultra power consumption. The proposed LNAs deliver 3dB power gains more than conventional folded cascode, while consuming 1.3mW dc power with an ultra low supply voltage of 0.6V.