A novel sort error hardened 10T SRAM cells for low voltage operation

In this paper, two types of a soft error hardened 10T SRAM cells with high static noise margin (SNM) are proposed for low voltage operation. The proposed NMOS stacked SRAM cell operates normally with higher read SNM near to sub-threshold region compared to prior works. Simulated results using 0.18um standard CMOS process demonstrate that proposed NMOS stacked-10T cell has high read SNM and high soft error resilience of at least 100 times higher than unprotected standard 6T SRAM cell for a single event transient (SET).