Design studies on the implementation of On Board Control, Signal Acquisition and Communication (OBCSAC) system on FPGA/ASIC platforms

The on board control, signal acquisition and communication (OBCSAC) subsystem is a critical component of all satellite systems. This paper presents the results of a feasibility study on realizing the design subsystem first on FPGA, and then on ASIC. Apart from giving the design details and results on a typical basic configuration, a number of extensions of this architecture have been studied and the results are presented. Specifically, starting from the realization of the basic configuration on a commercial antifuse FPGA, the studies carried out include (a) mapping the vital configuration onto an equivalent radiation hardened antifuse FPGA (b) mapping the same configuration onto a commercial FPGA after incorporating dasiaTriple Modular Redundancy (TMR) manually at the RTL level, (c) altering the basic architecture significantly to conform to the CCSDS standard prescribed for the OBCSAC of any satellite and mapping the design onto to FPGAs as well as on ASICS first without TMR and then separately incorporating TMR for each case. The basic configuration realized in an FPGA had been extensively tested in hardware under various expected environmental conditions and the FPGA utilization details are provided. For the ASIC design, the details up to the layout/GDSII stage are presented. Further, in the case of the ASIC, the test patterns for the netlist were generated based on ATPG software and the details of fault coverage are provided. The FPGA designs were carried out with Actel SX72A and AX1000 device families and the ASIC designs were carried out using the AMIS 0.35u CMOS libraries. The results presented in this work will serve as a design guideline in terms of FPGA/ASIC area, power, speed, and fault coverage and fault tolerance to those working in the area of system design.