Title :
New linearization method for low voltage, low power folded cascode LNAs
Author :
Zavarei, Mohammad Javad ; Kargaran, Ehsan ; Nabovati, Hooman
Author_Institution :
Dept. of Electr. Eng., Sadjad Inst. for Higher Educ., Mashhad, Iran
Abstract :
This paper presents a highly-linear, low power, low noise amplifier (LNA) using a novel nonlinearity cancellation technique by employing the folded cascode topology. The circuit functionality is analyzed using Volterra series analysis. The linear LNA was designed and simulated in a TSMC 0.18μm CMOS process at 5GHz frequency. By employing the new technique, the IIP3 is improved by more than 14dB compare to conventional folded cascode LNA reaching to +1dBm without any significant effect on the other LNA parameters. The proposed LNA also delivers a voltage gain (S21) of 12.4 dB with a noise figure of 3.9 dB, while consuming only 1.27 mW dc power with a low supply voltage of 0.6 V.
Keywords :
CMOS integrated circuits; Volterra series; low noise amplifiers; low-power electronics; CMOS process; IIP3; Volterra series analysis; circuit functionality; frequency 5 GHz; gain 12.4 dB; linear LNA; linearization method; low noise amplifier; low power folded cascode LNA; low voltage cascode LNA; noise figure 3.9 dB; nonlinearity cancellation technique; power 1.27 mW; size 0.18 micron; voltage 0.6 V; CMOS integrated circuits; CMOS technology; Low-noise amplifiers; Noise; Noise figure; Topology; Transistors;
Conference_Titel :
Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on
Conference_Location :
Boise, ID
Print_ISBN :
978-1-4673-2526-4
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2012.6292126
