Low-power 3rd-order continuous-time low-pass sigma-delta analog-to-digital converter for wideband applications

This paper presents the design of a low-power 3^rdorder continuous-time (CT) low-pass (LP) sigma-delta (ΣΔ) analog-to-digital converter (ADC) with 20 MHz bandwidth. The bandwidth of the system is large enough to accommodate LTE and other wideband wireless network standards. A 3^rd-order filter with feed-forward compensation is proposed to achieve low-power consumption and low complexity. A 3-bit flash quantizer is utilized to provide fast data conversion rate. The current-steering digital-to-analog converter (DAC) helps directly inject the feedback signal without additional circuitries. In order to avoid overall performance degradation from current glitches, cross-coupled transistors are adopted for the current steering DAC. The proposed system achieves a peak SNDR of 65.9 dB with 20 MHz bandwidth, a SFDR of 74.8 dBc, and a dynamic range (DR) of 62 dB, while it consumes 32.65 mW from a 1.8 V supply. The entire circuit is designed in a 0.18 μm CMOS technology and is driven by 500 MHz sampling rate.