Technique for frequency transfer over packet networks

This paper describes the design and performance analysis of a new approach for frequency synchronization over packet networks. The technique which includes a digital phase-locked loop (DPLL) is timestamp-based and involves a transmitter clock sending periodically an explicit time indication or timestamp to the receiver so that it can synchronize its local clock to that of the transmitter. The digital oscillator used in the PLL is a divide-by-N counter type oscillator (DNCO). We explain how the DPLL can be designed using standard control theory concepts and show how the DPLL performs in the presence of network perturbations like packet delay variations (PDV) which is the main source of clock errors in packet-based synchronization.