FPGA-based discrete ambiguity function for stochastic linear time-variant channels

This work presents a novel signal processing algorithm framework for the FPGA implementation of the discrete ambiguity function which is used as a tool for the modeling and simulation of randomly time-variant linear channels in multiple input multiple output, orthogonal frequency division multiplexing, communication systems applications. The discrete ambiguity function was implemented using, both, a Xilinx IP core for the efficient computation of the discrete Fourier transform, and a new scalable implementation of the Pease FFT algorithm which takes advantage of structural symmetries and regularities exhibited in the FFT formulations when presented in Kronecker products form. Important results show that this new scalable core outperforms the Xilinx IP core when it comes to latency and number of slices used.