• DocumentCode
    3207128
  • Title

    Fundamental performance constraints in horizontal fusion of in-order cores

  • Author

    Salverda, Pierre ; Zilles, Craig

  • Author_Institution
    Dept. of Comput. Sci., Univ. of Illinois at Urbana-Champaign, Urbana, IL
  • fYear
    2008
  • fDate
    16-20 Feb. 2008
  • Firstpage
    252
  • Lastpage
    263
  • Abstract
    A conceptually appealing approach to supporting a broad range of workloads is a system comprising many small cores that can be fused, on demand, into larger cores. We demonstrate that using in-order cores for this purpose, even under idealized assumptions about fusion-related overheads, would introduce fundamental obstacles to achieving good performance - obstacles that are not present when out-of-order cores are used. Matching the performance of modern dynamically-scheduled designs demands that a fused machine be able to simultaneously manage a large number of active dataflow chains, many more than the amount of ILP typically extracted from the code. When it is in-order cores that are fused, this requirement, in turn, demands either that the active dataflow chains be carefully interleaved among the available issue queues, or that enough cores be provided for them to reside at distinct queues. Using an abstract model for reasoning about the performance of these machines, we show that the former option is fundamentally hard, in the sense that it necessitates instruction steering hardware that would be too complex to build. The latter option would demand so many cores that the machine would be overwhelmed by fusion-related overheads. In short, if the goal is to match the performance of modern dynamically-scheduled machines, fusion of in-order cores is not a very compelling approach; either a fundamentally new method for fusing cores is needed, or some form of out-of-order capability must be provided at the constituent cores.
  • Keywords
    multiprocessing systems; processor scheduling; active dataflow chains; dynamically-scheduled designs; fused machine; fusion-related overheads; horizontal fusion; in-order cores; out-of-order cores; Clocks; Computer science; Graphics; Hardware; Out of order; Parallel processing; Physics computing; Resists; Signal processing; Signal synthesis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computer Architecture, 2008. HPCA 2008. IEEE 14th International Symposium on
  • Conference_Location
    Salt Lake City, UT
  • ISSN
    1530-0897
  • Print_ISBN
    978-1-4244-2070-4
  • Type

    conf

  • DOI
    10.1109/HPCA.2008.4658644
  • Filename
    4658644