A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS

Author

Huang, Ke ; Wang, Ziqiang ; Zheng, Xuqiang ; Ma, Xuan ; Yu, Kunzhi ; Zhang, Chun ; Wang, Zhihua

Author_Institution

Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China

fYear

2012

fDate

5-8 Aug. 2012

Firstpage

932

Lastpage

935

Abstract

In this paper, a novel clock and data recovery scheme for 10Gbps source synchronous receiver is presented in 65nm CMOS technology, which includes the implementation of a quadrature clock generation circuit and a 10Gbps CDR circuit. The quadrature clock generation circuit is based on an open loop delay line, avoiding the design of the complex DLL or PLL loop which is often used in source synchronous links. The 10Gbps CDR is based on phase interpolator, and a novel clock and data recovery algorithm is proposed to reduce jitter of the recovered clock. The power consumption is 25mW under 1.2V power supply.

Keywords

CMOS integrated circuits; clock and data recovery circuits; jitter; low-power electronics; phase locked loops; CMOS; DLL; PLL loop; bit rate 10 Gbit/s; clock recovery scheme; data recovery scheme; jitter reduction; open loop delay line; phase interpolator; power 25 mW; power consumption; quadrature clock generation circuit; size 65 nm; source synchronous link; source synchronous receiver; voltage 1.2 V; CMOS integrated circuits; Clocks; Computer architecture; Delay lines; Jitter; Phase locked loops; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on

Conference_Location

Boise, ID

ISSN

1548-3746

Print_ISBN

978-1-4673-2526-4

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2012.6292174

Filename

6292174