Title :
A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm CMOS
Author :
Yu, Kunzhi ; Wang, Ziqiang ; Ma, Xuan ; Zheng, Xuqiang ; Zhang, Chun ; Wang, Zhihua
Author_Institution :
Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
This paper describes a 6.4Gb/s data lane circuit in 65nm CMOS process. The data lane circuit consists of an offset cancellation continuous time linear equalizer and a half-rate digital CDR; the CDR bandwidth is programmable by using a digital FIR filter. A common-mode level shift function is implemented in order to use NMOS input CML circuit. The design can compensate over 8 dB channel loss with offset-calibrated and low noise. The area for one data lane is 0.045 μm2 and power consumption is 24.5mW for 1.2V supply.
Keywords :
CMOS digital integrated circuits; FIR filters; clock and data recovery circuits; current-mode logic; CDR bandwidth; CMOS process; NMOS input CML circuit; bit rate 6.4 Gbit/s; common-mode level shift function; data lane design; digital FIR filter; forwarded clock receiver; half-rate digital CDR; offset cancellation continuous time linear equalizer; power 24.5 mW; size 65 nm; voltage 1.2 V; Bandwidth; CMOS integrated circuits; Clocks; Equalizers; MOS devices; Receivers; Transceivers;
Conference_Titel :
Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on
Conference_Location :
Boise, ID
Print_ISBN :
978-1-4673-2526-4
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2012.6292175
