Pinning techniques for low-floor detection/decoding of LDPC-Coded partial response channels

There is a well-known error-floor phenomenon associated with iterative LDPC decoders which has delayed the use of LDPC codes in certain communication and storage systems. Error floors are known to generally be caused by so-called trapping sets, subsets of code bits which induce a subgraph in a codepsilas Tanner graph that have the effect of locking up the decoder. In earlier work, the authors proposed three decoder-based techniques that lower the LDPC error floors on binary-input AWGN channels. In this paper, we introduce two techniques that lower the error-rate floors for LDPC-coded partial response (PR) channels, which are applicable to magnetic and optical storage. The techniques involve, via external measures, ldquopinningrdquo one of the bits in each problematic trapping set and then letting the iterative decoder proceed to correct the rest of the bits. We present two classes of pinning solutions: (1) a pre-pinning technique which fixes (pins) selected trapping set bits prior to transmission and (2) a post-pinning approach which utilizes information from outer BCH decoders to pin bits in trapping sets. Our simulations on PR1 and EPR4 channels demonstrate that the floor for the code chosen for this study, a 0.78(2048,1600) quasi-cyclic LDPC code, is lowered by orders of magnitude, beyond the reach of simulations.