DocumentCode :
3207773
Title :
Hardware implementation of soft-decision decoding for Reed-Solomon code
Author :
Kan, Makiko ; Okada, Shogo ; Maehara, Takafumi ; Oguchi, Kazuhiro ; Yokokawa, Takashi ; Miyauchi, Toshiyuki
Author_Institution :
Sony Corp., Tokyo
fYear :
2008
fDate :
1-5 Sept. 2008
Firstpage :
73
Lastpage :
77
Abstract :
We implemented a soft-decision decoder of (204,188)-Reed-Solomon code, which is used widely in standards for satellite, terrestrial, and other broadcasting systems. The decoder employs a list decoding technique using iterative adaptive belief propagation and bounded distance decoding. One decoded word is chosen from the list by MAP decoding, and some ideas are applied to reduce its complexity. When the channel throughput is 32 Mbps, the decoder works at 88 MHz in an FPGA, and obtains 1 dB performance gain compared with ordinary hard-decision decoders.
Keywords :
Reed-Solomon codes; field programmable gate arrays; maximum likelihood decoding; FPGA; MAP decoding; Reed-Solomon code; bounded distance decoding; hardware implementation; iterative adaptive belief propagation; soft-decision decoding; Belief propagation; Hardware; Interpolation; Iterative decoding; Parity check codes; Performance gain; Reed-Solomon codes; Satellite broadcasting; Turbo codes; Variable speed drives;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Turbo Codes and Related Topics, 2008 5th International Symposium on
Conference_Location :
Lausanne
Print_ISBN :
978-1-4244-2862-5
Electronic_ISBN :
978-1-4244-2863-2
Type :
conf
DOI :
10.1109/TURBOCODING.2008.4658675
Filename :
4658675
Link To Document :
بازگشت