Title :
Scheduling and module assignment for reducing BIST resources
Author :
Parulkar, Ishwar ; Gupta, Sandeep K. ; Breuer, Melvin A.
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
Built-in self-test (BIST) techniques modify functional hardware to give a data path the capability to test itself. The modification of data path registers into registers (BIST resources) that can generate pseudo-random test patterns and/or compress test responses, incurs an area overhead penalty. We show how scheduling and module assignment in high-level synthesis affect BIST resource requirements of a data path. A scheduling and module assignment procedure is presented that produces schedules which, when used to synthesize data paths, result in a significant reduction in BIST area overhead and hence total area
Keywords :
built-in self test; circuit layout CAD; high level synthesis; integrated circuit testing; logic testing; scheduling; BIST area overhead reduction; BIST resources reduction; built-in self-test techniques; data path registers; data path synthesis; data path testing; high-level synthesis; module assignment; pseudo-random test patterns; scheduling; test response compression; Automatic testing; Built-in self-test; Hardware; High level synthesis; Libraries; Monitoring; Multiplexing; Multiprocessor interconnection networks; Registers; Test pattern generators;
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
DOI :
10.1109/DATE.1998.655838
