ATM traffic shaper: ATS

Author

Diaz, Juan Carlos ; Plaza, Pierre ; Crespo, Jesús

Author_Institution

Telefonica Investigacion y Desarrollo, Madrid, Spain

fYear

1998

fDate

23-26 Feb 1998

Firstpage

96

Lastpage

101

Abstract

The design and Implementation of an ATM Traffic Shaper (ATS) is described. This IC was realised on a 0.35 μm CMOS technology. The main function of the ATS is the collection of low bit rate traffic to fill a higher bit rate pipe in order to reduce the cost of ATM based services, nowadays mainly influenced by transmission cost. The circuit fits in several ATM system configurations but mainly will be used at the User-Network Interfaces or Network-Network interfaces. The IC was designed with a top-down methodology using as HDL, Verilog. The chip is pad limited and is encapsulated in a 208 PQFP package. The circuit complexity is 38 Kgates and its working frequency is 32 MHz. A circuit prototype was build with FPGAs in order to validate the RTL description

Keywords

CMOS digital integrated circuits; application specific integrated circuits; asynchronous transfer mode; circuit CAD; digital signal processing chips; field programmable gate arrays; integrated circuit design; logic CAD; telecommunication computing; telecommunication traffic; 0.35 micron; 32 MHz; ATM traffic shaper; ATS chip; CMOS technology; FPGAs; PQFP package; RTL description validation; Verilog; higher bit rate pipe; low bit rate traffic; network-network interfaces; top-down methodology; transmission cost reduction; user-network interfaces; Bit rate; CMOS integrated circuits; CMOS technology; Complexity theory; Cost function; Frequency; Hardware design languages; Packaging; Prototypes; Telecommunication traffic;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 1998., Proceedings

Conference_Location

Paris

Print_ISBN

0-8186-8359-7

Type

conf

DOI

10.1109/DATE.1998.655842

Filename

655842