DocumentCode :
3208078
Title :
A reduced-complexity box-plus decoder for LDPC codes
Author :
Viens, Matthew ; Ryan, William E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Arizona, Tucson, AZ
fYear :
2008
fDate :
1-5 Sept. 2008
Firstpage :
151
Lastpage :
156
Abstract :
The primary contribution of this paper is the full description of a new decoder for LDPC codes - the reduced-complexity box-plus (RCBP) decoder. This new decoder is based on the combination of two known decoding algorithms, the box-plus decoder and the a-min* decoder. What is new, however, is the check-node processor design which is based on a highly compressed look-up table. This compression exploits the symmetry and redundancy of the full table in order to losslessly reduce the 1024-element table to merely two easily implementable logic equations. Simulations of the RCBP decoder are compared to a low-complexity decoder patented by Flarion/Qualcomm. The RCBP decoder was found to be essentially equal in terms of bit error rate and frame error rate performance. Our analysis of the RCBP decoderpsilas speed and complexity indicate that it is superior to the Flarion/Qualcomm decoder in these aspects.
Keywords :
computational complexity; error statistics; parity check codes; Flarion-Qualcomm decoder; LDPC codes; a-min decoder; bit error rate; check-node processor design; frame error rate; reduced-complexity box-plus decoder; Decoding; Mercury (metals); Parity check codes; Turbo codes;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Turbo Codes and Related Topics, 2008 5th International Symposium on
Conference_Location :
Lausanne
Print_ISBN :
978-1-4244-2862-5
Electronic_ISBN :
978-1-4244-2863-2
Type :
conf
DOI :
10.1109/TURBOCODING.2008.4658689
Filename :
4658689
Link To Document :
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