DocumentCode :
320818
Title :
PSCP: A scalable parallel ASIP architecture for reactive systems
Author :
Pyttel, Andreas ; Sedlmeier, Alexander ; Veith, Christian
Author_Institution :
Corp. Technol., Siemens AG, Munich, Germany
fYear :
1998
fDate :
23-26 Feb 1998
Firstpage :
370
Lastpage :
376
Abstract :
We describe a codesign approach based on a parallel and scalable ASIP architecture, which is suitable for the implementation of reactive systems. The specification language of our approach is extended statecharts. Our ASIP architecture is scalable with respect to the number of processing elements as well as parameters such as bus widths and register file sizes. Instruction sets are generated from a library of components covering a spectrum of space/time trade-off alternatives. Our approach features a heuristic static timing analysis step for statecharts. An industrial example requiring the real-time control of several stepper motors illustrates the benefits of our approach
Keywords :
application specific integrated circuits; high level synthesis; instruction sets; microprocessor chips; parallel architectures; real-time systems; specification languages; timing; bus widths; codesign approach; extended statecharts; heuristic static timing analysis step; instruction sets; processing elements; reactive systems; real-time control; register file sizes; scalable parallel ASIP architecture; space/time trade-off alternatives; specification language; stepper motors; Application software; Application specific processors; Hardware; Instruction sets; Libraries; Optimization; Program processors; Software systems; Specification languages; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
Type :
conf
DOI :
10.1109/DATE.1998.655884
Filename :
655884
Link To Document :
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