Title :
Efficient minarea retiming of large level-clocked circuits
Author :
Maheshwari, Naresh ; Sapatnekar, Sachin S.
Author_Institution :
Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Abstract :
Delay-constrained area optimization is an important step in synthesis of VLSI circuits. Minimum area (minarea) retiming is a powerful technique to solve this problem. The minarea retiming problem has been formulated as a linear program; in this work we present techniques for reducing the size of this linear program and efficient techniques for generating it. This results in an efficient minarea retiming method for large level-clocked circuits (with tens of thousands of gates)
Keywords :
VLSI; circuit optimisation; clocks; delays; linear programming; sequential circuits; timing; VLSI circuits; delay-constrained area optimization; large level-clocked circuits; linear program; minarea retiming; minimum area retiming; retiming method; Circuit synthesis; Clocks; Delay; Design automation; Design optimization; Latches; Power engineering and energy; Power engineering computing; Timing; Very large scale integration;
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
DOI :
10.1109/DATE.1998.655956
