An approach to realistic fault prediction and layout design for testability in analog circuits

Author

Prieto, J.A. ; Rueda, A. ; Grout, I. ; Peralías, E. ; Huertas, J.L. ; Richardson, A.M.D.

Author_Institution

Inst. de Microelectron., Seville Univ., Spain

fYear

1998

fDate

23-26 Feb 1998

Firstpage

905

Lastpage

909

Abstract

This paper presents an approach towards realistic fault prediction in analog circuits. It exploits the Inductive Fault Analysis (IFA) methodology to generate explicit models able to give the probability of occurrence of faults associated with devices in an analog cell. This information intends to facilitate the integration of design and test phases in the development of an IC since it provides a realistic fault list for simulation before going to the final layout, and also makes possible layout optimization towards what we can call layout level design for testability

Keywords

analogue integrated circuits; design for testability; fault diagnosis; integrated circuit layout; integrated circuit modelling; probability; analog circuits; design for testability; explicit models; fault prediction; inductive fault analysis methodology; layout design; layout level DFT; layout optimization; probability; realistic fault list; Analog circuits; Analytical models; Circuit faults; Circuit simulation; Circuit testing; Costs; Design for testability; Fabrication; Predictive models; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 1998., Proceedings

Conference_Location

Paris

Print_ISBN

0-8186-8359-7

Type

conf

DOI

10.1109/DATE.1998.655965

Filename

655965