Architectural support for synchronization of threads accessing variable-sized units of virtual memory

The paper presents an architecture for synchronization of threads or tasks when accessing regions of virtual memory. Access control is defined on a memory region through a view that defines the size of access units and also the protocol in terms of a finite state machine (FSM). Variable-sized access units are obtained without altering the underlying fixed sized paging implementation. Trace-driven simulation is used to examine average delay for the PCU and to examine its performance when various parameters were varied. A TPC-C benchmark application under different transaction loads was traced and the results show that it is the number of TLB accesses (approximately 15 times more as compared to PCU accesses) for the modeled application that incurs the dominant delay