DocumentCode
3208775
Title
Secure and Authenticated Communication in Chip-Level Microcomputer Bus Systems with Tree Parity Machines
Author
Mühlbach, Sascha ; Wallner, Sebastian
Author_Institution
Hamburg Univ. of Technol., Hamburg
fYear
2007
fDate
16-19 July 2007
Firstpage
201
Lastpage
208
Abstract
The protection of chip-level microcomputer bus systems in embedded devices is essential to prevent the growing number of hardware hacking attacks. This paper presents an authenticated key exchange and encryption solution in order to ensure chip-level microcomputer bus systems via the tree parity machine rekeying architecture (TPMRA). Due to this intention, a scalable TPMRA IP-core is designed and implemented in order to meet variable bus performance requirements. It allows the authentication of the bus participants as well as the encryption of chip-to-chip buses from a single primitive. The solution is transparent and easy applicable to an arbitrary microcomputer bus system for embedded devices on the market. A proof of concept implementation shows the applicability of the TPMRA in the standardized advanced microprocessor bus architecture (AMBA) by implementing the IP-core into the peripheral bus-to-bus interface (AHB-APB-bridge). It will be shown that the solution is latency free and can be used in order to protect the ARM bus system with a low hardware overhead considering all AMBA bus features.
Keywords
computer architecture; cryptography; microprocessor chips; system buses; AHB-APB-bridge; TPMRA IP-core; advanced microprocessor bus architecture; authenticated communication; authenticated key exchange; chip-level microcomputer bus systems; chip-to-chip buses; embedded devices; encryption; hardware hacking attacks; peripheral bus-to-bus interface; secure communication; tree parity machine rekeying architecture; tree parity machines; Communication system control; Computer hacking; Cryptography; Data mining; Delay; Embedded computing; Engines; Hardware; Microcomputers; Protection; AMBA Bus; Embedded Security; Secure Bus Systems; System-on-Chip; Tree Parity Machines;
fLanguage
English
Publisher
ieee
Conference_Titel
Embedded Computer Systems: Architectures, Modeling and Simulation, 2007. IC-SAMOS 2007. International Conference on
Conference_Location
Samos
Print_ISBN
1-4244-1058-4
Type
conf
DOI
10.1109/ICSAMOS.2007.4285752
Filename
4285752
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