DocumentCode :
3209122
Title :
Optimizing replication, communication, and capacity allocation in CMPs
Author :
Chishti, Zeshan ; Powell, Michael D. ; Vijaykumar, T.N.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fYear :
2005
fDate :
4-8 June 2005
Firstpage :
357
Lastpage :
368
Abstract :
Chip multiprocessors substantially increase capacity pressure on the on-chip memory hierarchy while requiring fast access. Neither private nor shared caches can provide both large capacity and fast access in CMPs. We observe that compared to symmetric multiprocessors (SMPs), CMPs change the latency capacity tradeoff in two significant ways. We propose three novel ideas to exploit the changes: (1) Through placing copies close to requestors allows fast access for read-only sharing, the copies also reduce the already-limited on-chip capacity in CMPs. We propose controlled replication to reduce capacity pressure by not making extra copies in some cases, and obtaining the data from an existing on-chip copy. This option is not suitable for SMPs because obtaining data from another processor is expensive and capacity is not limited to on-chip storage. (2) Unlike SMPs, CMPs allow fast on-chip communication between processors for read-write sharing. Instead of incurring slow access to read-write shared data through coherence misses as do SMPs, we propose in situ communication to provide fast access without making copies or incurring coherence misses. (3) Accessing neighbor´s caches is not as expensive in CMPs as it is in SMPs. We propose capacity stealing in which private data that exceeds a core´s capacity is placed in a neighboring cache with less capacity demand. To incorporate our ideas, we use a hybrid of private, per-processor tag arrays and a shared data array. Because the shared data is slow, we employ non-uniform access and distance associativity from previous proposals to hold frequently-accessed data in regions close to the requestor. We extend the previously-proposed non-uniform access with replacement and placement using distance associativity (NuRAPID) ro CMPs, and call our cache CMP-NuRAPID. Our result show that for a 4-core CMP with 8 MB cache, CMP-NuRAPID improves performance by 13% over a shared cache and 8% over private caches for three commercial multithreaded workloads.
Keywords :
cache storage; microprocessor chips; multi-threading; parallel processing; read-only storage; shared memory systems; storage allocation; CMP-NuRAPID; capacity allocation; chip multiprocessors; coherence misses; commercial multithreaded workloads; distance associativity; latency capacity tradeoff; on-chip communication; on-chip memory hierarchy; on-chip storage; per-processor tag arrays; read-only sharing; read-write sharing; replication; shared caches; shared data array; symmetric multiprocessors; Costs; Delay effects; Pressure control; Proposals; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Architecture, 2005. ISCA '05. Proceedings. 32nd International Symposium on
ISSN :
1063-6897
Print_ISBN :
0-7695-2270-X
Type :
conf
DOI :
10.1109/ISCA.2005.39
Filename :
1431570
Link To Document :
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