DocumentCode :
3209369
Title :
Exploiting structural duplication for lifetime reliability enhancement
Author :
Srinivasan, Jayanth ; Adve, Sarita V. ; Bose, Pradip ; Rivers, Jude A.
Author_Institution :
Dept. of Comput. Sci., Univ. of Illinois at Urbana-Champaign, IL, USA
fYear :
2005
fDate :
4-8 June 2005
Firstpage :
520
Lastpage :
531
Abstract :
Increased power densities (and resultant temperatures) and other effects of device scaling are predicted to cause significant lifetime reliability problems in the near future. In this paper, we study two techniques that leverage microarchitectural structural redundancy for lifetime reliability enhancement. First, in structural duplication (SD), redundant microarchitectural structures are added to the processor and designated as spares. Spare structures can be turned on when the original structure fails, increasing the processor´s lifetime. Second, graceful performance degradation (GPD) is a technique which exploits existing microarchitectural redundancy for reliability. Redundant structures that fail are shut down while still maintaining functionality, thereby increasing the processor´s lifetime, but at a lower performance. Our analysis shows that exploiting structural redundancy can provide significant reliability benefits, and we present guidelines for efficient usage of these techniques by identifying situations where each is more beneficial. We show that GPD is the superior technique when only limited performance or cost resources can be sacrificed for reliability. Specifically, on average for our systems and applications, GPD increased processor reliability to 1.42 times the base value for less than a 5% loss in performance. On the other hand, for systems where reliability is more important than performance or cost, SD is more beneficial. SD increases reliability to 3.17 times the base value for 2.25 times the base cost, for our applications. Finally, a combination of the two techniques (SD+GPD) provides the highest reliability benefit.
Keywords :
computer architecture; configuration management; program control structures; program processors; reliability theory; SD+GPD; device scaling; graceful performance degradation; lifetime reliability enhancement; lifetime reliability problem; microarchitectural structural redundancy; power density; processor lifetime; processor reliability; redundant microarchitectural structure; resultant temperature; spare structure; structural duplication; system reliability; Computer science; Costs; Degradation; Guidelines; Maintenance; Microarchitecture; Process design; Redundancy; Rivers; Temperature;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Architecture, 2005. ISCA '05. Proceedings. 32nd International Symposium on
ISSN :
1063-6897
Print_ISBN :
0-7695-2270-X
Type :
conf
DOI :
10.1109/ISCA.2005.28
Filename :
1431583
Link To Document :
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