DocumentCode :
3209697
Title :
A general technique for deterministic model-cycle-level debugging
Author :
Khan, Asif ; Vijayaraghavan, Muralidaran ; Arvind
Author_Institution :
Comput. Sci. & Artificial Intell. Lab., Massachusetts Inst. of Technol., Cambridge, MA, USA
fYear :
2012
fDate :
16-17 July 2012
Firstpage :
109
Lastpage :
118
Abstract :
Efficient use of FPGA resources requires FPGA-based performance models of complex hardware to implement one model cycle, i.e., one time-step of the original synchronous system, in several implementation cycles. Generally implementation cycles have no simple relationship with model cycles, and it is tricky to reconstruct the state of the synchronous system at the model-cycle boundaries if only implementation-cycle-level control and information is provided. A good debugging facility needs to provide: complete control over the functioning of the target design being simulated; fast and easy access to all the significant target design state for both monitoring and modification; and some means of accomplishing deterministic execution when the target design is a multicore processor running a parallel application. Moreover, these features need to be provided in a manner which does not incur substantial resource and performance penalties. In this paper, we present a debugging technique based on the LI-BDN theory. We show how the technique facilitates deterministic model-cycle-level debugging. We used it to build the debugging infrastructure for Arete, which is an FPGA-based cycle-accurate multicore simulator. The resource and performance penalties of our debugging technique are minimal; in Arete the debugging infrastructure has area and performance overheads of 5% and 6%, respectively.
Keywords :
digital simulation; field programmable gate arrays; multiprocessing systems; parallel processing; program debugging; Arete; FPGA resources; FPGA-based cycle-accurate multicore simulator; FPGA-based performance models; LI-BDN theory; deterministic execution; deterministic model-cycle-level debugging; general technique; implementation-cycle-level control; multicore processor; parallel application; Debugging; Field programmable gate arrays; Monitoring; Random access memory; Registers; Synchronization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Formal Methods and Models for Codesign (MEMOCODE), 2012 10th IEEE/ACM International Conference on
Conference_Location :
Arlington, VA
Print_ISBN :
978-1-4673-1314-8
Type :
conf
DOI :
10.1109/MEMCOD.2012.6292307
Filename :
6292307
Link To Document :
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