A novel buried lightly doped drain CMOS design for optimizing hot carrier versus device performance

A novel and unique buried lightly doped drain (BLDD) design for nMOSFET technology is demonstrated in this paper. This design significantly reduces the maximum electric field at the drain edge thus lowering hot carrier degradation while minimizing the impact on key transistor parameters. This unique buried LDD design could be used to improve current as well as future CMOS device technologies. Although sub 90 nm technologies require less hot carrier protection, but still could benefit from this approach as a way to reduce gate-assisted band-to-band tunneling, which increases transistor and diode leakage of these devices