A new low voltage four-quadrant current mode multiplier

Author

Kaedi, Saman ; Farshidi, Ebrahim

Author_Institution

Dept. of Electr. & Comput. Eng., Chamran Univ. of Technol., Ahvaz, Iran

fYear

2012

fDate

15-17 May 2012

Firstpage

160

Lastpage

164

Abstract

In this paper a new CMOS current-mode multiplier based on squarer circuit is proposed. The dual translinear loop is the basic building block in realization scheme. Supply voltage is 1.8 V. The major advantages of this multiplier are low voltage, high speed, low power, immunity of body effect, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator by level 49 parameters in 0.18μm CMOS technology. The simulation results of analog multiplier demonstrate a THD of 1.24% in 1MHz, a -3dB bandwidth of 31.2MHz and power consumption is less than 207 μW.

Keywords

CMOS analogue integrated circuits; analogue multipliers; current-mode circuits; harmonic distortion; low-power electronics; CMOS current-mode multiplier; CMOS technology; HSPICE simulator; THD; analog multiplier; bandwidth 31.2 MHz; body effect immunity; dual translinear loop; frequency 1 MHz; low voltage four-quadrant current mode multiplier; power consumption; size 0.18 mum; squarer circuit; total harmonic distortion; voltage 1.8 V; CMOS integrated circuits; CMOS technology; Software; Current mode; Multiplier; Quadrant; Squarer circuit; Translinear loop;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering (ICEE), 2012 20th Iranian Conference on

Conference_Location

Tehran

Print_ISBN

978-1-4673-1149-6

Type

conf

DOI

10.1109/IranianCEE.2012.6292344

Filename

6292344