Title :
New routing and compaction strategies for yield enhancement
Author :
Chiluvuri, Venkat K R ; Koren, Israel
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
Improvements in manufacturing lines alone can not compensate for the yield losses due to the increase in complexity of logic. Manufacturing yield improvement needs to be addressed during the physical layout synthesis stage itself. Several layout strategies for yield enhancement are proposed and they are illustrated with respect to channel compaction and routing in standard cell design. Algorithms and other implementation issues are discussed and examples illustrating these algorithms are presented
Keywords :
cellular arrays; circuit layout CAD; logic CAD; network routing; channel compaction; compaction strategies; complexity of logic; layout strategies; manufacturing lines; physical layout synthesis stage; routing; standard cell design; yield enhancement; yield losses; Algorithm design and analysis; Compaction; Computer aided manufacturing; Design automation; Electric variables; Fault tolerant systems; Logic; Minimization methods; Routing; Wire;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1992. Proceedings., 1992 IEEE International Workshop on
Conference_Location :
Dallas, TX
Print_ISBN :
0-8186-2837-5
DOI :
10.1109/DFTVS.1992.224342
