Title :
Best methods to minimize latch-up sensitivities in semiconductor circuits
Author :
Naughton, John ; Tyler, Matthew
Author_Institution :
AMIS Technol. R&D, Pocatello, ID
Abstract :
Latch-up occurs when two bipolar transistor structures enter a self-sustained low impedance state between the anode and cathode. This condition is often the result of parasitic PNP and NPN structures inherent to CMOS circuits. It is possible to predict the latch-up threshold and therefore exercise sound layout techniques to avoid triggering parasitic SCR structures under normal operating conditions
Keywords :
CMOS integrated circuits; bipolar transistors; integrated circuit layout; integrated circuit testing; CMOS circuits; NPN structures; PNP structure; bipolar transistor structure; latch-up sensitivity; parasitic SCR structures; self-sustained low impedance state; semiconductor circuits; Ambient intelligence; Bipolar transistors; CMOS technology; Circuit testing; Electronic equipment testing; Integrated circuit testing; MOSFETs; Qualifications; Thyristors; Voltage;
Conference_Titel :
Microelectronics and Electron Devices, 2005. WMED '05. 2005 IEEE Workshop on
Conference_Location :
Boise, ID
Print_ISBN :
0-7803-9072-5
DOI :
10.1109/WMED.2005.1431631
