An improved BIRA for memories with optimal repair rate using a flipping analyzer

With the advance of technology, integration in chip level and the resulting decrease in size of embedded memories on SOCs, the probability of memory defects has also increased, resulting in yield drop. Built-in Redundancy Analysis (BIRA) is a solution to solve this problem by replacing faulty cells with good cells. In this paper a new BIRA approach with optimal repair rate using flipping-analyzer is presented. Existing parallel techniques suffer from high area overhead. The proposed BIRA implemented by flipping-analyzers breaks down the analysis process into two phases without any complicated FSM to load different solutions to BIRA. The proposed method achieves a short analysis time and low area overhead in memories with symmetric redundancy configuration. It can save 50% of area overhead compared with other parallel BIRAs. Also it is faster than IntelligentSolveFirst and ESP methods.