DocumentCode
3210546
Title
A new 8-transistors floating full-adder circuit
Author
Shiri Asmangerdi, Nabiallah ; Forounchi, J. ; Ghanbari, K.
Author_Institution
Microelectron. & Microsensor Lab., Tabriz Univ., Tabriz, Iran
fYear
2012
fDate
15-17 May 2012
Firstpage
194
Lastpage
197
Abstract
In this paper, a new high-speed full adder cell called “Floating full adder” has been proposed. This design offers a full adder with 8 transistors which its internal nodes are not directly connected to the ground. Simulations have been performed by Hspice software based on 90nm CMOS model, BSIM4 (level 54) version 4.4. Simulation results show that suggested circuit has maximum propagation delay equal to 33pS and average dissipation power of 87.53μW and PDP of 2.89fJ at 1GHz input signals frequency, which shows the circuit has low power dissipation at high speeds.
Keywords
CMOS logic circuits; MOSFET; adders; integrated circuit modelling; BSIM4 version 4.4; CMOS model; Hspice software; energy 2.89 fJ; frequency 1 GHz; high-speed full adder cell; low power dissipation; maximum propagation delay; power 87.53 muW; size 90 nm; transistors floating full-adder circuit; Adders; CMOS integrated circuits; CMOS technology; Delay; Standards; Floating full adder; high speed; low power;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Engineering (ICEE), 2012 20th Iranian Conference on
Conference_Location
Tehran
Print_ISBN
978-1-4673-1149-6
Type
conf
DOI
10.1109/IranianCEE.2012.6292351
Filename
6292351
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