DocumentCode :
3210628
Title :
Negative bias temperature instability in triple gate transistors
Author :
Maeda, Shigenobu ; Choi, Jung A. ; Yang, Jeong-Hwan ; Jin, You-Seung ; Bae, Su-Kon ; Kim, Young-Wug ; Suh, Kwang-Pyuk
Author_Institution :
Technol. Dev. Team, Samsung Electron., Gyeonggi-Do, South Korea
fYear :
2004
fDate :
25-29 April 2004
Firstpage :
8
Lastpage :
12
Abstract :
Negative bias temperature instability (NBTI) in triple gate transistors was investigated for the first time. It is found that the threshold voltage shift caused by negative bias temperature stress in conventional configuration of triple gate transistors is worse than that in planar transistors. This is due to the larger trap state density of the [110] side surface of the active silicon and it is verified by comparing two types of triple gate transistors each of which has [110] side surface and (100) side surface. The <100>-direction channel is proposed as one of the structural options to reduce the degradation of NBTI in triple gate transistors.
Keywords :
MOSFET; dangling bonds; interface states; larger trap state density; negative bias temperature instability; planar transistors; side surface; threshold voltage shift; triple gate transistors; Annealing; Degradation; Etching; MOSFETs; Negative bias temperature instability; Niobium compounds; Silicon; Stress; Titanium compounds; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International
Print_ISBN :
0-7803-8315-X
Type :
conf
DOI :
10.1109/RELPHY.2004.1315293
Filename :
1315293
Link To Document :
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