Title :
System Level Optimization of Static Power Consumption in Nano-CMOS Circuits
Author_Institution :
Oldenburg Research and Development Institute for Information Technology Tools and Systems, Escherweg 2, 26121 Oldenburg, Germany. E-mail: domenik.helms@offis.de
Abstract :
Recent design techniques reducing leakage currents at all levels of abstraction are presented. Leakage reduction techniques can be divided by their applicability and the abstraction level into 3 main classes [1]: improved devices, trade off techniques, and leakage management. This work will detail on each of these classes.
Keywords :
CMOS integrated circuits; integrated circuit design; leakage currents; nanotechnology; leakage current reduction techniques; leakage management; nano-CMOS circuit design; static power consumption; system level optimization; trade off techniques; Circuits; Control systems; Energy consumption; Energy management; Gate leakage; High K dielectric materials; High-K gate dielectrics; Leakage current; Power system management; Voltage; CMOS; Leakage; Static power;
Conference_Titel :
Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07. 14th International Conference on
Conference_Location :
Ciechocinek
Print_ISBN :
83-922632-9-4
Electronic_ISBN :
83-922632-9-4
DOI :
10.1109/MIXDES.2007.4286143
