Title :
A 3.4 GB/S Low Latency 1 Bit Input Digital FIR-Filter in 0.13 μM CMOS
Author :
Fredriksson, H. ; Svensson, C. ; Alvandpour, A.
Author_Institution :
Linkoping Univ., Linkoping
Abstract :
This paper presents a low latency, one bit input, high-speed FIR-filter designed for multi-Gb/s mixed signal decision feedback equalizers. The filter utilizes a carry-save FIR tap structure and an efficient dual-edge-flip-flop-multiplexer. The filter has been implemented in a standard 0.13 μm CMOS technology. Simulation results from extracted layout shows correct functionality up to 3.4 G words/s with a latency ≪280 ps.
Keywords :
CMOS digital integrated circuits; FIR filters; feedback; flip-flops; CMOS technology; bit rate 3.4 Gbit/s; digital FIR-fIlter; dual-edge-flip-flop-multiplexer; signal decision feedback equalizers; size 0.13 μm; storage capacity 1 bit; CMOS technology; Decision feedback equalizers; Delay; Digital filters; Finite impulse response filter; Nonlinear filters; Parasitic capacitance; Signal design; Table lookup; Temperature; CMOS; FIR; Gb-IO; carry-save; equalizer;
Conference_Titel :
Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07. 14th International Conference on
Conference_Location :
Ciechocinek
Print_ISBN :
83-922632-4-3
Electronic_ISBN :
83-922632-9-4
DOI :
10.1109/MIXDES.2007.4286146
