Hierarchical approach for design of application specific logic controller

In the paper, a structured synthesis method based on hierarchical Petri nets is presented. An implemented design framework contains the programmable logic synthesis of rule-based descriptions that are obtained from several specification models of concurrent controllers, especially in control interpreted Petri net format. The specification in the form of symbolic conditional decision rules is transformed into a format that is accepted by standard FPGA simulators and synthesizers, such as Xilinx Foundation Series. The concurrent state machine model of logic controller is verified using the well-developed Petri net theory, and then it is translated through automated processes into selected FPGA specification format, e.g. Xilinx netlist format (XNF). Proposed technique is illustrated by presenting a solution to the popular “drill station” problem. The methods are especially useful in designing of industrial application specific logic controller (ASLC) with FPGA