Title :
A Kick-Back Reduced Comparator for a 4-6-Bit 3-GS/s Flash ADC in a 90nm CMOS Process
Author :
Sundström, T. ; Alvandpour, A.
Author_Institution :
Linkoping Univ. of Technol., Linkoping
Abstract :
This paper presents a kick-back reduced comparator based on a sense-amplifier type comparator. The kickback charge and resulting voltage peak is reduced by 6times, which corresponds to a power reduction in the input driver and the resistance ladder of the same magnitude. A 4-6-bit 3-GS/s low-power flash ADC using the proposed comparator has been implemented in a 90 nm CMOS process. The significantly lower requirements on input driver and resistance ladder have reduced the overall ADC power dissipation by 50%.
Keywords :
CMOS integrated circuits; amplifiers; analogue-digital conversion; comparators (circuits); ladder networks; ADC power dissipation; CMOS process; kickback reduced comparator; power reduction; resistance ladder; sense-amplifier type comparator; CMOS process; CMOS technology; Clocks; Costs; Energy consumption; Impedance; Inverters; Power dissipation; Testing; Voltage; CMOS; Comparator; Flash ADC; Kick-back; Low-power;
Conference_Titel :
Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07. 14th International Conference on
Conference_Location :
Ciechocinek
Print_ISBN :
83-922632-9-4
Electronic_ISBN :
83-922632-9-4
DOI :
10.1109/MIXDES.2007.4286149
